This invention relates to a field effect transistor and more particularly to a manufacturing method of a field effect transistor device whose substrate is prepared from gallium arsenide (GaAs) semiconductor material.
Field effect transistors prepared from gallium arsenide are widely accepted as semiconductor elements constituting important circuit elements involved in high frequency amplifiers and oscillators. Recently, IC devices comprised of GaAs FETs have assumed greater importance due to their various merits.
The high frequency index Pf of a GaAs FET is expressed as EQU Pf.varies.Cgs/gm
where,
Cgs: stray capacitance between the gate and source of the GaAs FET PA1 gm: transconductance of the FET PA1 gm0: true transconductance primarily defined by the physical property of the channel region of the GaAs FET PA1 R.sub.s : series resistance between the source and gate of the GaAs FET
It is seen from the above formula that the object of improving the high frequency property of the GaAs FET is attained by reducing the stray capacitance Cgs between the gate and source of the GaAs FET and/or increasing the transconductance of the FET. As is well known, the transconductance gm of the FET is further defined as: EQU gm=gm0/(1+gm0.multidot.R.sub.s)
where,
It is seen from the above formula that the improvement of the transconductance of the FET has to be attained by reducing the series resistance R.sub.s between the source and gate of the GaAs FET and/or enlarging the true transconductance gm0 itself. Enlargement of the true transconductance gm0 can be effected by shortening the gate. The foregoing discussion shows that it is necessary for the improvement of the high frequency property of the GaAs FET to reduce the series resistance R.sub.s between the source and gate of the GaAs FET and/or shorten the gate as much as possible.
Further, it is necessary to pay attention to the gate-drain withstand voltage property as an important parameter in studying the performance of the GaAs FET. Now let it be assumed that when a high frequency amplifier is formed of, for example, GaAs FETs, the drain voltage is set at 3 volts, and the pinch-off voltage is set at -2 volts. Then a maximum voltage of 5 volts is impressed on the gate-drain region of one FET gate. Naturally, the breakdown voltage (rating) of the gate-drain region of the GaAs FET should be higher than at least 5 volts. With respect to a high output type high frequency amplifier, it should obviously be taken into account that the gate-drain breakdown voltage of the GaAs FET is demanded to be higher than 10 volts.
Hitherto, difficulties have been encountered in manufacturing a GaAs FET which can be improved to such a level that requirements for the above-mentioned two properties (that is, the high frequency property of the GaAs FET and its high breakdown voltage) can be satisfied at the same time. For instance, it is assumed that the conventional fabrication technique encounters considerable difficulties in trying to shorten the gate length of the GaAs FET to a submicron level in order to realize the improvement of the GaAs FET. Considered in terms of pure technique, it may be possible to shorten the gate length to a submicron level, for example, 0.5 micron. However, the electron irradiation process still has a low wafer-processing capacity. The X-ray lithography is not yet perfected. If, therefore, the manufacturing cost is taken into account, these processes cannot be expected to effect the mass production of satisfactory GaAs FETs. Further, it is well known among those skilled in the art to carry out ion implantation with a metal gate layer on the substrate used as a mask and provide source and drain regions self-aligned with the gate. According to this process, the conductance gm can be increased due to a decrease in the series resistance R.sub.s between the source and gate. This contributes to the improvement of the high frequency properties of FETs. Nevertheless, conventional self-aligned FETs still encounter the difficulties that since the source and drain regions of said FET are simply set adjacent to the metal gate, the distances between the gate and source and also between the gate and drain, are shortened. Consequently, the breakdown voltage property of the gate-drain regions is undesirably deteriorated. In other words, it has hitherto been impossible to simultaneously improve the high frequency and the source-drain breakdown voltage properties of GaAs FETs.
A description may now be made of another approach to the resolution of the aforementioned problems, that is, a "recess structure" type device which is intended to minimize the series resistance R.sub.s between the source region and gate layer. As used herein, the term "recess structure" is defined to mean a specific operational layer whose surface portion positioned under a gate electrode is etched and made thinner. However, the recess structure is still accompanied with the drawbacks that the fabrication of part of the aforementioned operational layer into a specific shape is difficult for the present day etching technique, and it is impossible to provide a recess structure bearing a satisfactory shape which allows for high shape controllability and high reproducibility.